1. Field of the Invention
The present invention relates to programmable logic memory cells, and in particular to a memory cell that eliminates problems associated with over erasure in both the read and the program cycles.
2. Description of the Related Art
Electrically erasable programmable read only memory (EEPROM) cells are well known in the art. Referring to FIG. 1, an EEPROM cell 100 includes an access transistor 101 and a storage transistor 102 having a floating gate 103 insulated from but capacitively coupled to a control gate 104. Storage transistor 102 is programmed by Fowler-Nordheim tunneling of electrons from drain D, through a thin oxide region 105, to a floating gate 103. Repeated programming of EEPROM cell 100 results in the trapping of some electrons in the thin oxide region, thereby resulting in a more negative threshold voltage after erasure. In this manner, electron trapping in EEPROM cell 100 eventually renders the cell inoperable.
Flash memory cells are also well known in the art. FIG. 2 illustrates a flash memory cell 200 having a split gate configuration, wherein the access transistor 202 and storage transistor 201 are merged into a single device with a channel region 210 shared by both transistors. Flash memory cell 200 is programmed by hot electron injection from the substrate to floating gate 203, and is erased by Fowler-Nordheim tunneling from floating gate 203, through thin oxide region 205, to drain D. Flash memory cell 200 solves the negative threshold voltage problem of EEPROM 100. Specifically, if the erase threshold voltage of storage transistor 201 becomes negative, the application of zero volts to control gate 204 may turn on storage transistor 201. However, because access transistor 202 is formed in series with storage transistor 201, memory cell 200 has a threshold voltage of approximately 1 volt and therefore as a device does not turn on. Unfortunately, because channel length 210 is not self-aligned during etching, this length may vary from cell to cell. This variation increases programming time as well as the probability of punch through (wherein the drain-source voltage is very high which causes the gate to lose control over the drain current).
Referring to FIGS. 3A and 3B, U.S. Pat. No. 5,329,487, issued to Gupta et al. on Jul. 12, 1994, discloses a prior art flash memory cell 300 which includes a standard floating gate transistor 302 and a merged transistor 304. Merged transistor 304 can be considered a floating gate transistor in series with an NMOS transistor, wherein one edge of a cell selection gate 312 of the NMOS transistor is aligned with a floating gate 311 of the floating gate transistor. The coupling ratio between cell selection gate 312 and floating gate 311 determines the amount of charge transferred to floating gate 311. Therefore, because alignment varies between memory cells, the coupling ratio also undesirably varies, thereby adversely affecting performance of the PLD.
Moreover, Gupta et al. teach providing a common source line 314 for access transistor 312 and storage transistor 311, thereby slowing down the speed of the PLD. Specifically, during logic operation of a PLD, any number of wordlines (WL) in the memory array can be high depending on the logic functions to be implemented in the PLD. Thus, it logically follows that any number of memory cells 300 are simultaneously conducting. The sense amplifiers (not shown), which detect the state of memory cells 300 via their associated bitlines (Read lines), can be pulled down by only one or all memory cells in a column.
To provide a fast response from the sense amplifier even with only one memory cell conducting, the sense amplifier has to be very sensitive, i.e. detecting a voltage drop on the bitline of approximately 50 mV. The maximum bitline drop for one memory cell conducting is 100 mV. On the other extreme, in the event that all memory cells are conducting, the voltage drop on the bitline becomes much more pronounced. Consequently, the time for the bitline to recover to the original state to perform sensing during the next logic state cycle depends strongly on the number of memory cells conducting during the read operation, and the speed of the PLD is limited by the longest possible recovery time. Thus, memory cell 300 fails to achieve the speed and flexibility required for high speed PLD applications.
Therefore, a need arises for a memory cell which eliminates the over-erase problems of the prior art while providing high speed PLD performance.